PLL



 


The multiplier VCXO is phase locked to a Racal 9420 5MHz reference using an MC145151 parallel input PLL chip. Fixed division counters are hardwired for both the reference and VCXO dividers. For a 10 368.750 MHz beacon output, the reference is exactly 5 MHz. Other frequencies are achieved by off-setting the 5 MHz reference.

Two-point modulation is used for the 400 Hz FSK keying, hence the key input to the loop op-amp in addition to the 5 MHz standard modulation.
synthpcb



Circuit diagram

beaconsynth

Modulation



                               
pll4          pll1   
pll3
   



  VXO modulation





 Reference modulation






 Combined modulation

 


                                                                                                                                                                                                                                                                                                                    The PLL loop frequency response and the keying modulation rate are sufficiently similar to make keying of either the VXO or reference oscillator alone inadequate. By modulating both the VXO and the reference (by the same amount), the loop error voltage remains constant despite the keying, and the transient reponse of the loop becomes irrelevent.

The combined modulation picture shows a slight inbalance of VXO and  Reference modulation.

This 'two point' modulation was pretty much universal in the days of PMR FM transceivers, since in that situation also there was also a need to have a relatively low reference frequency (dictated by the channel spacing requirement) combined with an acceptably quick channel change time.